136 lines
2.4 KiB
NASM
136 lines
2.4 KiB
NASM
global idt_init
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extern handle_isr
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%macro ISR_NOERR 1
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isr_stub_%1:
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push qword 0
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push qword %1
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jmp isr_common
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%endmacro
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%macro ISR_ERR 1
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isr_stub_%1:
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push qword %1
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jmp isr_common
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%endmacro
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section .bss
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align 4096
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idt64:
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resb 4096
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section .data
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align 8
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isr_stub_table:
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%assign i 0
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%rep 256
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dq isr_stub_%[i]
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%assign i i+1
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%endrep
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idt64_descriptor:
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dw 4095
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dq idt64
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section .text
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bits 64
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idt_init:
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; Fill in the idt table with the stub functions
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mov rdi, idt64
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mov rsi, isr_stub_table
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mov rcx, 256
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.loop:
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mov rax, [rsi]
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mov [rdi], ax
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mov word [rdi + 2], 0x08
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mov word [rdi + 4], 0x8E00
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shr rax, 16
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mov [rdi + 6], ax
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shr rax, 16
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mov [rdi + 8], eax
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mov dword [rdi + 12], 0
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add rdi, 16
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add rsi, 8
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loop .loop
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lidt [idt64_descriptor]
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ret
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isr_common:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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mov rdi, rsp
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call handle_isr
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop rbp
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pop rdi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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add rsp, 16
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iretq
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; CPU exceptions 0-31. Some of these contain error codes, so we define them manually
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ISR_NOERR 0
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ISR_NOERR 1
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ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_ERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_NOERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_ERR 30
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ISR_NOERR 31
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; Hardware interrupts and user-defined interrupts (32-255). These don't have error codes
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%assign i 32
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%rep 224
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ISR_NOERR i
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%assign i i+1
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%endrep |