291 lines
5.8 KiB
NASM
291 lines
5.8 KiB
NASM
global _start
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extern kmain
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extern handle_isr
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extern pml4
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%define FLAGS 0b10
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%define MAGIC 0x1BADB002
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%define CHECKSUM -(MAGIC + FLAGS)
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section .multiboot
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align 4
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dd MAGIC
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dd FLAGS
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dd CHECKSUM
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section .bss
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align 16
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resb 32768
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stack_top:
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section .bss
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align 4096
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pml4:
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resb 4096
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pdpt:
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resb 4096
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pd:
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resb 4096
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section .data
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align 8
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gdt64:
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dq 0x0000000000000000
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.code:
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dq 0x00AF9A000000FFFF
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.descriptor:
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dw .end - gdt64 - 1
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dq gdt64
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.end:
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section .data
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align 8
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multiboot_info:
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dq 0
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section .text
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bits 32
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_start:
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mov esp, stack_top
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; Multiboot will place a magic value in eax
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; If this magic value is not present, then we might not have multiboot info in ebx,
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; therefore we throw an error
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cmp eax, 0x2BADB002
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jne error
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; Save multiboot info pointer for later
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mov [multiboot_info], ebx
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; Check if cpuid is available by flipping bit 21
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; in the eflags register and checking if the cpu flipped it back
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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; If cpuid is available, eax should be different than ecx
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xor eax, ecx
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jz error
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; Finally restore eflags register to the original value
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push ecx
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popfd
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; Check if extended cpuid is available by calling cpuid with 0x80000000,
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; If cpuid is available, eax will be greater than 0x80000000 after the call
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb error
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; Check if long mode is available by calling cpuid with 0x80000001
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; this will place the extended features of the cpu in edx
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; Bit 29 tells us if long mode is supported or not
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29
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jz error
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; Enable PAE by setting bit 5 in cr4 to 1
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; pml4[0] -> pdpt
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mov eax, pdpt
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or eax, 0x03
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mov [pml4], eax
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; pdpt[0] -> pd
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mov eax, pd
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or eax, 0x03
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mov [pdpt], eax
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; Map first 32 2mb pages for the kernel for a total of 64mb
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mov edi, pd
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mov eax, 0x83
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mov ecx, 32
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.setup_pd:
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mov [edi], eax
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add eax, 0x200000
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add edi, 8
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loop .setup_pd
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; Load cr3 with the address of pml4
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mov eax, pml4
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mov cr3, eax
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lgdt [gdt64.descriptor]
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; Enable long mode by setting bit 8 to 1 in EFER (Extended Feature Enable Register)
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mov ecx, 0xc0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; Enable paging by setting bit 31 in cr0 to 1
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mov eax, cr0
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or eax, 1 << 31
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mov cr0, eax
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jmp 0x8:long_mode
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error:
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cli
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mov byte [0xb8000], 'E'
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mov byte [0xb8002], 'R'
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mov byte [0xb8004], 'R'
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.hang:
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hlt
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jmp .hang
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section .bss
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align 4096
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idt64:
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resb 4096
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section .data
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align 8
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idt64_descriptor:
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dw 4095
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dq idt64
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section .data
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align 8
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isr_stub_table:
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%assign i 0
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%rep 256
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dq isr_stub_%[i]
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%assign i i+1
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%endrep
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%macro ISR_NOERR 1
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isr_stub_%1:
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push qword 0
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push qword %1
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jmp isr_common
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%endmacro
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%macro ISR_ERR 1
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isr_stub_%1:
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push qword %1
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jmp isr_common
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%endmacro
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section .text
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bits 64
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long_mode:
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; Clear segment registers in long mode
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xor ax, ax
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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; Fill in the idt table with the stub functions
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mov rdi, idt64
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mov rsi, isr_stub_table
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mov rcx, 256
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.loop:
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mov rax, [rsi]
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mov [rdi], ax
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mov word [rdi + 2], 0x08
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mov word [rdi + 4], 0x8E00
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shr rax, 16
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mov [rdi + 6], ax
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shr rax, 16
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mov [rdi + 8], eax
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mov dword [rdi + 12], 0
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add rdi, 16
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add rsi, 8
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loop .loop
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lidt [idt64_descriptor]
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; Finally, we call in to c
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mov rdi, [multiboot_info]
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call kmain
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.hang:
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hlt
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jmp .hang
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isr_common:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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mov rdi, rsp
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call handle_isr
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop rbp
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pop rdi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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add rsp, 16
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iretq
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; CPU exceptions 0-31. Some of these contain error codes, so we define them manually
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ISR_NOERR 0
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ISR_NOERR 1
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ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_ERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_NOERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_ERR 30
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ISR_NOERR 31
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; Hardware interrupts and user-defined interrupts (32-255). These don't have error codes
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%assign i 32
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%rep 224
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ISR_NOERR i
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%assign i i+1
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%endrep |